log · ·Text to PCB

Parsing netlists from text descriptions

The parser reads a domain-specific language where each line declares a component or a connection. Components are identified by reference designator and footprint; connections are listed as net names followed by the pins they join.

The output is a graph of components and nets that the placement and routing stages consume directly. Most of the work this week was handling the edge cases: implicit power nets, ground planes that should be inferred rather than declared, and multi-pin components where not every pin appears in the netlist.

Power net handling is still fragile. If a component has a VCC pin but the netlist never mentions VCC, the parser currently warns and leaves it unconnected. The right behavior is probably to infer a power rail, but that requires knowing which pins are power pins — which means the footprint library needs to carry that metadata.